Electrical isolation of semiconductor integrated transistors from one another can be achieved by laterally (in the plane of the wafer) isolating "active" regions of the device with insulating material. Two techniques are common: 1) selectively oxidizing wafer silicon surrounding the active region by means of Local Oxidation of Silicon (LOCOS), or the like, or 2) depositing insulating material, such as silicon dioxide ("oxide") in a trench (or "bathtub") formed around the active regions.
Regarding the latter technique (trench formation and filling), trenches are typically etched (e.g. plasma etched) into the substrate around the active regions to a depth "d" of from a few hundred Angstroms (.ANG.) to a few microns (.mu.m). A patterned mask, such as silicon dioxide or silicon nitride, is used for etching the trenches, and an etchant such as fluorine and/or chlorine containing gases, are normally used for etching the substrate selectively (preferentially) to the mask material. Commonly, the resulting trenches are overfilled with silicon dioxide ("oxide"), and excess oxide (that which is not within the trench) is removed, such as by polishing--as disclosed in commonly-owned, copending U.S. patent application Ser. No. 07/711,634.
FIG. 1 shows a semiconductor device 110, including a substrate 112. A trench 114 is formed around a diffusion (active) region 116. The trench is either filled (not shown) by a Chemical Vapor Deposition (CVD) process with an insulating material, such as silicon dioxide ("oxide"), or (as shown) oxide 118 can be thermally formed in the trench. In either case, an oxide isolation structure is formed around the diffusion region.
In either case, the oxide isolation structures are created early on in the device fabrication process, and all subsequent processing is aligned to them. The size and shape of the oxide structure is not solely determined by the requirements for isolation, but can also be significantly affected by the processes used to generate the structures. It is not uncommon for the isolation size to be determined by the ability to create the pattern for the isolation and the subsequent oxide growth process.
The placement of the process used to create the oxide isolation in the processing scheme is significantly determined by the "root (DT)" of the process--that is the heat cycle's time and temperature, required to grow the necessary thermal oxide in an oxygen ambient. The application of this high temperature process can only be accommodated early on in the process, before the introduction (implantation into the diffusion region) of atomic species, e.g., boron or phosphorous, which have large diffusion coefficients. The diffusion of these "fugitive" species at the high temperature of silicon dioxide oxidation has well known detrimental effects on the electrical characteristics of the subsequently created active elements and structures, such as transistors. Among these detrimental effects is that subsequent diffusion (i.e., migration) of the fugitive species must be accounted for, which results in larger and hence slower active elements. Hereinafter, any and all active elements formed in or on the diffusion region will be referred to as "transistors", since they are the most common active element.
As mentioned above, it is also possible to create isolation structures using Chemical Vapor Deposition (CVD) processes to create the silicon dioxide structures. These materials retain most of the positive virtues of the thermally grown oxide isolation structures, but are not typically as free of particles, nor as free of ionic contamination. Nonetheless, they are adequate, especially if a relatively thin thermally grown oxide (500-1000 .ANG.) underlies the CVD oxide. These CVD isolation structures are typically inserted into the transistor device process flow in the same process flow location as the thermally grown oxide--in other words, early on in the process flow (prior to implantation). As such, the isolation structure is determined before the transistor comes into existence.
Returning to FIG. 1, it is known to provide various implants 120a (e.g., source), 120b (e.g., drain) and/or deposited structures 120c (e.g., gate) in and on the diffusion region 116. These implants and structures are shown generically, to indicate a patterned transistor device formed in the diffusion region. A circuit element, such as a transistor, having been created in the diffusion region, and bounded by an oxide isolation structure 118, it is known to provide a subsequent dielectric layer 124, such as CVD Borophosphosilicate glass (BPSG) overlying the transistor structure 120a-c and isolation structures 118. The formation of this passivation layer 124 represents an additional (i.e., second) dielectric fabrication step and, significantly, another thermal step which is subsequent to transistor formation.